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Quad-Channel Digital Isolators ADuM1410/ADuM1411/ADUM1412
FEATURES
Low power operation 5 V operation 1.3 mA per channel max @ 0 Mbps to 2 Mbps 4.0 mA per channel max @ 10 Mbps 3 V operation 0.8 mA per channel max @ 0 Mbps to 2 Mbps 1.8 mA per channel max @ 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/s 16-lead, Pb-free, SOIC wide body package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity (pending) DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 DISABLE 7 GND1 8
ADuM1410
ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE
16 15 14 13 12 11 10 9
VDD2 GND2 VOA VOB VOC VOD
06502-001
CTRL GND2
Figure 1. ADuM1410 Functional Block Diagram
VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 VOD 6 CTRL1 7 GND1 8
16 15
ADuM1411
ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE
VDD2 GND2 VOA VOB VOC VID
06502-002 06502-003
14 13 12 11 10 9
CTRL2 GND2
Figure 2. ADuM1411 Functional Block Diagram
VDD1 1 GND1 2 VIA 3 VIB 4 VOC 5 VOD 6 CTRL1 7 GND1 8
16 15
APPLICATIONS
General-purpose multichannel isolation SPI(R) interface/data converter isolation RS-232/RS-422/RS-485 transceiver Industrial field bus isolation
ADUM1412
ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE ENCODE
VDD2 GND2 VOA VOB VIC VID CTRL2 GND2
14 13 12 11 10 9
Figure 3. ADUM1412 Functional Block Diagram
GENERAL DESCRIPTION
The ADuM141x1 are four-channel digital isolators based on Analog Devices, Inc. iCoupler(R) technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products.
1
Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM141x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM141x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.
Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents pending. Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADuM1410/ADuM1411/ADUM1412 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Operation................................ 3 Electrical Characteristics--3 V Operation................................ 5 Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 7 Package Characteristics ............................................................. 10 Regulatory Information............................................................. 10 Insulation and Safety-Related Specifications.......................... 10 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics ............................................................................ 11 Absolute Maximum Ratings ......................................................... 12 Recommended Operating Conditions .................................... 12 ESD Caution................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 16 Application Information................................................................ 18 PC Board Layout ........................................................................ 18 Propagation Delay-Related Parameters................................... 18 DC Correctness and Magnetic Field Immunity........................... 18 Power Consumption .................................................................. 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
10/06--Rev. D to Rev. E Added ADuM1411 and ADUM1412................................Universal Deleted ADuM1310 ...........................................................Universal Changes to Features.......................................................................... 1 Changes to Specifications Section.................................................. 3 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 3/06--Rev. C to Rev. D Added Note 1 and Changes to Figure 2......................................... 1 Changes to Absolute Maximum Ratings ..................................... 11 11/05--Rev. SpB to Rev. C: Initial Version
Rev. E | Page 2 of 20
ADuM1410/ADuM1411/ADUM1412 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V OPERATION
4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. 1 Table 1.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM1410, Total Supply Current, Four Channels 2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM1411, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADUM1412, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Symbol IDDI (Q) IDDO (Q) Min Typ 0.50 0.38 Max 0.73 0.53 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
2.4 1.2 8.8 2.8
3.2 1.6 12 4.0
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
2.2 1.8 5.4 3.8
2.8 2.4 7.6 5.3
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q), IDD2 (Q) IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH VIL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL -10
2.0 4.6 +0.01
2.6 6.5 +10
mA mA A
DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA,VIB, VIC,VID VDD1 or VDD2, 0 VCTRL1,VCTRL2 VDD1 or VDD2, VDISABLE VDD1
Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages
2.0 0.8 VDD1, VDD2 - 0.1 VDD1, VDD2 - 0.4 5.0 4.8 0.0 0.04 0.2
0.1 0.1 0.4
V V V V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM1411ARW and ADUM1412ARW Minimum Pulse Width 3 Maximum Data Rate 4 Propagation Delay 5 Pulse Width Distortion, |tPLH - tPHL|5 Propagation Delay Skew 6 Channel-to-Channel Matching 7
PW tPHL, tPLH PWD tPSK tPSKCD/OD 1 20 65
1000 100 40 50 50
ns Mbps ns ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. E | Page 3 of 20
ADuM1410/ADuM1411/ADUM1412
Parameter ADuM141xBRW Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5 Pulse Width Distortion, |tPLH - tPHL|5 Change vs. Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 8 Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate Input Enable Time 9 Input Disable Time9 Input Dynamic Supply Current per Channel 10 Output Dynamic Supply Current per Channel10
1 2
Symbol PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
Min
Typ
Max 100
Unit ns Mbps ns ns ps/C ns ns ns
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
10 20
30 5
50 5 30 5 6
tR/tF |CMH| |CML| fr tENABLE tDISABLE IDDI (D) IDDO (D)
25 25
2.5 35 35 1.2 2.0 5.0 0.12 0.04
ns kV/s kV/s Mbps s s mA/Mbps mA/Mbps
CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V VIA, VIB, VIC, VID, = 0 or VDD1 VIA, VIB, VIC, VID, = 0 or VDD1
All voltages are relative to their respective ground. The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADUM1412 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10). 10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 4 of 20
ADuM1410/ADuM1411/ADUM1412
ELECTRICAL CHARACTERISTICS--3 V OPERATION
2.7 V VDD1 3.6 V, 2.7 V VDD2 3.6 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 3.0 V. 1 Table 2.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM1410, Total Supply Current, Four Channels 2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM1411, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADUM1412, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRW Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Symbol IDDI (Q) IDDO (Q) Min Typ 0.25 0.19 Max Unit 0.38 mA 0.33 mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
1.2 0.8 4.5 1.4
1.6 1.0 6.5 1.8
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
1.0 0.9 3.1 2.1
1.9 1.7 4.5 3.0
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q), IDD2 (Q) IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH VIL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL -10
1.0 2.6
1.8 3.8
mA mA A
DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA,VIB, VIC,VID VDD1 or VDD2, 0 VCTRL1,VCTRL2 VDD1 or VDD2, VDISABLE VDD1
+0.01 +10
Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages
1.6 0.4 VDD1, VDD2 - 0.1 3.0 VDD1, VDD2 - 0.4 2.8 0.0 0.04 0.2
0.1 0.1 0.4
V V V V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM1411ARW and ADUM1412ARW Minimum Pulse Width 3 Maximum Data Rate 4 Propagation Delay 5 Pulse Width Distortion, |tPLH - tPHL|5 Propagation Delay Skew 6 Channel-to-Channel Matching 7 ADuM141xBRW Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5
PW tPHL, tPLH PWD tPSK tPSKCD/OD PW tPHL, tPLH 10 20 40 1 20 75
1000 ns Mbps 100 ns 40 ns 50 ns 50 ns 100 60 ns Mbps ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. E | Page 5 of 20
ADuM1410/ADuM1411/ADUM1412
Parameter Pulse Width Distortion, |tPLH - tPHL|5 Change vs. Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 8 Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate Input Enable Time 9 Input Disable Time9 Input Dynamic Supply Current per Channel 10 Output Dynamic Supply Current per Channel10
1 2
Symbol PWD tPSK tPSKCD tPSKOD
Min
Typ 5
Max Unit 5 ns ps/C 30 ns 5 ns 6 ns
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tR/tF |CMH| |CML|
25 25
2.5 35 35 1.1 2.0 5.0 0.07 0.02
ns kV/s kV/s
CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
tENABLE tDISABLE IDDI (D) IDDO (D)
Mbps s VIA, VIB, VIC, VID = 0 or VDD1 s VIA, VIB, VIC, VID = 0 or VDD1 mA/Mbps mA/Mbps
All voltages are relative to their respective ground. The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADUM1412 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10). 10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 6 of 20
ADuM1410/ADuM1411/ADUM1412
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation 1 : 4.5 V VDD1 5.5 V, 2.7 V VDD2 3.6 V; 3 V/5 V operation: 2.7 V VDD1 3.6 V, 4.5 V VDD2 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADuM1410, Total Supply Current, Four Channels 2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM1411, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADUM1412, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Symbol IDDI (Q) 0.50 0.25 IDDO (Q) 0.19 0.38 0.33 mA 0.53 mA 0.73 mA 0.38 mA Min Typ Max Unit Test Conditions
IDD1 (Q) 2.4 1.2 IDD2 (Q) 0.8 1.2 IDD1 (10) 8.6 3.4 IDD2 (10) 1.4 2.6 1.8 3.0 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 11 6.5 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 1.0 1.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 3.2 1.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (Q) 2.2 1.0 IDD2 (Q) 0.9 1.7 IDD1 (10) 5.4 3.1 IDD2 (10) 2.1 3.8 3.0 5.3 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 7.6 4.5 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 1.7 2.4 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 2.8 1.9 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (Q) 2.0 1.0 IDD2 (Q) 1.0 2.0 1.8 2.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 2.6 1.8 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
Rev. E | Page 7 of 20
ADuM1410/ADuM1411/ADUM1412
Parameter 10 Mbps (BRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation For All Models Input Currents Symbol IDD1 (10) 4.6 2.6 IDD2 (10) 2.6 4.6 IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH -10 +0.01 3.8 6.5 +10 mA mA A 5 MHz logic signal frequency 5 MHz logic signal frequency 0 VIA,VIB, VIC,VID VDD1 or VDD2, 0 VCTRL1,VCTRL2 VDD1 or VDD2, VDISABLE VDD1 6.5 3.8 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency Min Typ Max Unit Test Conditions
Logic High Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages
2.0 1.6 VIL 0.8 0.4 VOAH, VOBH, VDD1, VDD2 - 0.1 VOCH, VODH VDD1, VDD2 - 0.4 VOAL, VOBL, VOCL, VODL VDD1, VDD2 VDD1, VDD - 0.2 0.0 0.1 0.04 0.1 0.2 0.4
V V V V V V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM1411ARW and ADUM1412ARW Minimum Pulse Width 3 Maximum Data Rate 4 Propagation Delay 5 Pulse Width Distortion, |tPLH - tPHL|5 Propagation Delay Skew 6 Channel-to-Channel Matching 7 ADuM141xBRW Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5 Pulse Width Distortion, |tPLH - tPHL|5 Change vs. Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Codirectional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output 8 Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Enable Time 9
PW tPHL, tPLH PWD tPSK tPSKCD/OD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD 10 25 35 5 1 25 70
1000 ns Mbps 100 ns 40 ns 50 ns 50 ns 100 60 5 30 5 6 ns Mbps ns ns ps/C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tR/tf 2.5 2.5 35 35 ns ns kV/s kV/s
CL = 15 pF, CMOS signal levels
|CMH| |CML| fr
25 25
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
tENABLE
1.2 1.1 2.0
Rev. E | Page 8 of 20
Mbps Mbps s
VIA, VIB, VIC, VID = 0 or VDD1
ADuM1410/ADuM1411/ADUM1412
Parameter Input Disable Time9 Input Dynamic Supply Current per Channel10 5 V Operation 3 V Operation Output Dynamic Supply Current per Channel10 5 V Operation 3 V Operation
1 2
Symbol tDISABLE IDDI (D)
Min
Typ 5.0 0.12 0.07
Max Unit s mA/Mbps mA/Mbps mA/Mbps mA/Mbps
Test Conditions VIA, VIB, VIC, VID = 0 or VDD1
IDDI (D) 0.04 0.02
All voltages are relative to their respective ground. The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADUM1412 channel configurations. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (See Table 10). 10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. E | Page 9 of 20
ADuM1410/ADuM1411/ADUM1412
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2
1 2
Symbol RI-O CI-O CI JCI JCO
Min
Typ 1012 2.2 4.0 33 28
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz Thermocouple located at center of package underside
The ADuM141x device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM141x have been approved by the organizations listed in Table 5. Table 5.
UL 1 Recognized under 1577 component recognition program1
1 2
CSA Approved under CSA Component Acceptance Notice #5A
VDE 2 (ADuM1411 and ADUM1412 pending) Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012
In accordance with UL1577, each ADuM141x is proof tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A). In accordance with DIN EN 60747-5-2, each ADuM141x is proof tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Value 2500 L(I01) 7.7 min L(I02) Unit Conditions V rms 1 minute duration mm Measured from input terminals to output terminals, shortest distance through air 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. E | Page 10 of 20
ADuM1410/ADuM1411/ADUM1412
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
These isolators are suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN EN 60747-5-2 approval. Table 7.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS
1
Conditions
Symbol
Characteristic I to IV 1 I to III I to II 40/105/21 2 560 1050
Unit
VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure; see Figure 7
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak V peak V peak
VIO = 500 V
TS IS1 IS2 RS
150 265 335 >109
C mA mA
See DIN VDE 0110 for definition of Classification 1 through Classification IV listed in the Characteristic column.
Rev. E | Page 11 of 20
ADuM1410/ADuM1411/ADUM1412 ABSOLUTE MAXIMUM RATINGS
Ambient temperature (TA) = 25C, unless otherwise noted. Table 8.
Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages1 (VDD1, VDD2) Input Voltages1, 2 (VIA, VIB, VIC, VID, VE1, VE2) Output Voltages1, 2 (VOA, VOB, VOC, VOD) Average Output Current per Pin3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients4
1 2
Rating -65C to +150C -40C to +105C -0.5 V to +7.0 V -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V -18 mA to +18 mA -22 mA to +22 mA -100 kV/s to +100 kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Table 9.
Parameter Operating Temperature Supply Voltages Input Signal Rise and Fall Times Symbol TA VDD1, VDD2 Min -40 2.7 Max +105 5.5 1.0 Unit C V ms
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 7 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage.
ESD CAUTION
Table 10. Truth Table (Positive Logic)
VIX Input 1 H L X X X CTRL Input 2 X X H or NC L H or NC VDISABLE State 3 L or NC L or NC H H X VDDI State 4 Powered Powered X X Unpowered VDDO State 5 Powered Powered Powered Powered Powered VOX Output1 H L H L H Notes Normal operation, data is high. Normal operation, data is low. Inputs disabled. Outputs are in the default state as determined by CTRL. Inputs disabled. Outputs are in the default state as determined by CTRL. Input unpowered. Outputs are in the default state as determined by CTRL. Outputs return to input state within 1 s of VDDI power restoration. See the Pin Configurations and Function Descriptions section for more details. Input unpowered. Outputs are in the default state as determined by CTRL. Outputs return to input state within 1 s of VDDI power restoration. See the Pin Configurations and Function Descriptions section for more details. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 s of VDDO power restoration. See the Pin Configurations and Function Descriptions section for more details.
X
L
X
Unpowered Powered
L
X
X
X
Powered
Unpowered Z
1 2 3
VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). CTRL refers to the CTRL signal on the input side of a given channel (A, B, C, or D). Available only on ADuM1410. 4 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 5 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
Rev. E | Page 12 of 20
ADuM1410/ADuM1411/ADUM1412 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 DISABLE 7 GND1* 8
16 VDD2 15 GND2*
ADuM1410
TOP VIEW (Not to Scale)
14 VOA 13 VOB 12 VOC 11 VOD 10 CTRL 9
GND2*
06502-005
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 4. ADuM1410 Pin Configuration
Table 11. ADuM1410 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 VID Logic Input D. 7 DISABLE Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state determined by CTRL. 8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 10 CTRL Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and VOD outputs are high when CTRL is high or disconnected and VDD1 is off. VOA, VOB, VOC, and VOD outputs are low when CTRL is low and VDD1 is off. When VDD1 power is on, this pin has no effect. 11 VOD Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. E | Page 13 of 20
ADuM1410/ADuM1411/ADUM1412
VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 VOD 6 CTRL1 7 GND1* 8
16 15
VDD2 GND2* VOA VOB VOC VID CTRL2 GND2*
06502-006
ADuM1411
TOP VIEW (Not to Scale)
14 13 12 11 10 9
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 5. ADuM1411 Pin Configuration
Table 12. ADuM1411 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 VOD Logic Output D. 7 CTRL1 Default Output Control. Controls the logic state the outputs assume when the input power is off. VOD output is high when CTRL1 is high or disconnected and VDD2 is off. VOD output is low when CTRL1 is low and VDD2 is off. When VDD2 power is on, this pin has no effect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 10 CTRL2 Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, and VOC outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. 11 VID Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. E | Page 14 of 20
ADuM1410/ADuM1411/ADUM1412
VDD1 1 GND1* 2 VIA 3 VIB 4 VOC 5 VOD 6 CTRL1 7 GND1* 8
16 15
VDD2 GND2* VOA VOB VIC VID CTRL2 GND2*
06502-007
ADUM1412
TOP VIEW (Not to Scale)
14 13 12 11 10 9
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADUM1412 Pin Configuration
Table 13. ADUM1412 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 VOD Logic Output D. 7 CTRL1 Default Output Control. Controls the logic state the outputs assume when the input power is off. VOC and VOD outputs are high when CTRL1 is high or disconnected and VDD2 is off. VOC and VOD outputs are low when CTRL1 is low and VDD2 is off. When VDD2 power is on, this pin has no effect. 8 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. 9 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 10 CTRL2 Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA and VOB outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. 11 VID Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. 16 VDD2 Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. E | Page 15 of 20
ADuM1410/ADuM1411/ADUM1412 TYPICAL PERFORMANCE CHARACTERISTICS
350 1.4 1.2
CURRENT/CHANNEL (mA)
300
SAFETY-LIMITING CURRENT (mA)
250
SIDE #2
1.0 0.8 5V 0.6 0.4 3V 0.2 0 0 2 4 6 DATA RATE (Mbps) 8 10
200
150
SIDE #1
100 50 0 0 50 100 150 CASE TEMPERATURE (C) 200
06502-004
Figure 7. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2
2.0
Figure 10. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
10
8
CURRENT/CHANNEL (mA)
1.5
CURRENT (mA)
6
5V 1.0
4
5V
3V 0.5
2 3V
06502-008
0
2
4 6 DATA RATE (Mbps)
8
10
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 8. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3 V Operation
1.0 0.9 0.8 CURRENT/CHANNEL (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1
06502-009
Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
10
8
CURRENT (mA)
5V
6
4
3V
5V 2 3V
0
2
4 6 DATA RATE (Mbps)
8
10
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 9. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Rev. E | Page 16 of 20
06502-012
0
0
06502-011
0
0
06502-010
ADuM1410/ADuM1411/ADUM1412
10 10
8
8
CURRENT (mA)
6
CURRENT (mA)
6
4 5V 2 3V 0 0 2 4 6 DATA RATE (Mbps) 8 10
4 5V 2 3V
06502-013
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
10
Figure 15. Typical ADUM1412 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
8
CURRENT (mA)
6
4 5V 2 3V
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
06502-014
0
Rev. E | Page 17 of 20
06502-015
0
ADuM1410/ADuM1411/ADUM1412 APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM141x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1, and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
VDD1 GND1 VIA VIB VIC VID DISABLE GND1 VDD2 GND2 VOA VOB VOC VOD CTRL GND2
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 2 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit. The magnetic field immunity of the ADuM141x is determined by the changing magnetic field which induces a voltage in the transformer's receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM141x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt) rn2; n = 1, 2, ... , N where: is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM141x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.
100
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
06502-018
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition.
INPUT (VIX) 50%
tPLH
OUTPUT (VOX)
tPHL
50%
06502-017
10
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values, and it is an indication of how accurately the timing of the input signal is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM141x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM141x components operating under the same conditions.
1
0.1
0.01
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 18. Maximum Allowable External Magnetic Flux Density
Rev. E | Page 18 of 20
06502-019
0.001 1k
ADuM1410/ADuM1411/ADUM1412
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and was of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM141x transformers. Figure 19 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM141x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current needed to be placed 5 mm away from the ADuM141x to affect the operation of the component.
1000 MAXIMUM ALLOWABLE CURRENT (kA) DISTANCE = 1m 100
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM141x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) x (2f - fr) + IDDI (Q) f 0.5 fr f > 0.5 fr
For each output channel, the supply current is given by IDDO = IDDO (Q)
-3
f 0.5 fr
IDDO = (IDDO (D) + (0.5 x 10 ) x CL x VDDO) x (2f - fr) + IDDO (Q) f > 0.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable Current for Various Current-to-ADuM141x Spacings
Rev. E | Page 19 of 20
06502-020
0.01
To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1410/ADuM1411/ADUM1412 channel configurations.
ADuM1410/ADuM1411/ADUM1412 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16 9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.50 (0.0197) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADuM1410BRWZ1 ADuM1410BRWZ-RL1 Number of Inputs, VDD1 Side 4 4 Number of Inputs, VDD2 Side 0 0 1 1 1 1 2 2 2 2 Maximum Data Rate 10 Mbps 10 Mbps Maximum Propagation Delay, 5 V 50 ns 50 ns 100 ns 100 ns 50 ns 50 ns 100 ns 100 ns 50 ns 50 ns Maximum Pulse Width Distortion 5 ns 5 ns 40 ns 40 ns 5 ns 5 ns 40 ns 40 ns 5 ns 5 ns Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description 16-Lead SOIC_W, Wide Body 16-Lead SOIC_W, Wide Body, 13" Reel 16-Lead SOIC_W, Wide Body 16-Lead SOIC_W, Wide Body, 13" Reel 16-Lead SOIC_W, Wide Body 16-Lead SOIC_W, Wide Body, 13" Reel 16-Lead SOIC_W, Wide Body 16-Lead SOIC_W, Wide Body, 13" Reel 16-Lead SOIC_W, Wide Body 16-Lead SOIC_W, Wide Body, 13" Reel Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16
3 ADuM1411ARWZ1 ADuM1411ARWZ-RL1 3 3 ADuM1411BRWZ1 13 ADuM1411BRWZ-RL 2 ADUM1412ARWZ1 ADUM1412ARWZ-RL1 2 2 ADUM1412BRWZ1 ADUM1412BRWZ-RL1 2
1
1 Mbps 1 Mbps 10 Mbps 10 Mbps 1 Mbps 1 Mbps
10 Mbps 10 Mbps
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06502-0-10/06(E)
Rev. E | Page 20 of 20
060606-A

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